TI TPS65982

參考如下連結:
http://www.ti.com/product/TPS65982/datasheet

Features

• USB Power Delivery (PD) Controller
  • Mode Configuration for Provider (Host), Consumer (Device), or Consumer-Provider
  • Bi-Phase Marked Encoding/Decoding (BMC)
  • Physical Layer (PHY) Protocol
  • Policy Manager
  • Configurable at Boot and Host-Controlled
• USB Type-C Specification 1.1 Compliance
  • Attach of USB Cable at Port
  • Cable Orientation and Role Detection
  • Assign CC and VCONN Pins
  • Advertise 1.5 A or 3 A for Type-C Power
• Port Power Switch
  • 5-V, 3-A Switch to VBUS for Type-C Power
  • 5- to 20-V, 3-A Bidirectional Switch to or from VBUS for USB PD Power
  • 5-V, 600-mA Switches for VCONN
  • Over-Current Limiter, Overvoltage Protector
  • Slew Rate Control
  • Hard Reset Support
• Port Data Multiplexer
  • USB 2.0 HS Data, UART Data, and Low Speed Endpoint
  • Auxiliary and Alternate Modes (DisplayPort and Vendor-Defined Modes)
• Power Management
  • Gate Control and Current Sense for External 5- to 20-V, 5-A NMOS FET Bidirectional Switch
  • Power Supply from 3.3-V, 5-V, or VBUS Source
  • 3.3-V LDO Output for Dead Battery Support
• BGA MicroStar Junior Package
  • 0.5-mm Pitch
  • Through-Hole Via Compatible for All Pins

Applications

• Notebook Computers
• Tablets and Ultrabooks
• Docking Systems
• DisplayPort and HDMI Dongles & Cables
• Charger Adapters
• USB PD Hosts, Devices, and Dual-Role Ports
• USB PD-Enabled Bus-Powered Devices

Description

The TPS65982 is a stand-alone USB Type-C & PD controller providing cable plug and orientation detection at the USB Type-C connector. Upon cable detection, the TPS65982 communicates on the CC wire using the USB Power Delivery (PD) protocol. When cable detection and USB PD negotiation are complete, the TPS65982 enables the appropriate power path and configures alternate mode settings for internal and (optional) external multiplexers.

The mixed-signal front end on the CC pins advertises 1.5 A or 3 A for Type-C power providers, detects a plug event and determines the USB Type-C cable orientation, and autonomously negotiates USB PD contracts by adhering to the specified bi-phase marked coding (BMC) and physical layer (PHY) protocol.

The port power switch can pass up to 3 A downstream at 5 V for legacy and Type-C USB power. An additional bidirectional switch path can provide USB PD power up to 3 A at a maximum of 20 V as either a provider (host), consumer (device), or provider-consumer.

The TPS65982 can also be a Downstream-Facing Port (DFP), Upstream-Facing Port (UFP), or Dual-Role Port (DRP) for data. The port data multiplexer can pass data to or from the top or bottom D+/D- signal pair at the port for USB 2.0 HS or UART and has a USB 2.0 Low Speed Endpoint. Additionally, the Sideband Use (SBU) signal pair is used for auxiliary or alternate modes of communication (DisplayPort or vendor-defined modes, for example).

The power management circuitry can utilize a 3.3-V or 5-V power supply inside the system, and also use VBUS to start up and negotiate power for a dead battery or no battery condition.

16.0 I2C Interface
 The TPS65982 has three I2C interface ports. I2C Port 1 is comprised of the I2C_SDA1,
 I2C_SCL1, and I2C_INT1 pins. I2C Port 2 is comprised of the I2C_SDA2, I2C_SCL2, and
 I2C_INT2 pins. These interfaces provide general status information about the TPS65982, as
 well as the ability to control the TPS65982 behavior, as well as providing information about
 connections detected at the USB-C receptacle and supporting communications to/from a
 connected device and/or cable supporting BMC USB-PD. The third port is comprised of the
 DEBUG_CTL1 and DEBUG_CTL2 pins. This third port is always a master and has no
 interrupt. This port is intended to master another device that has simple control based on mode
 and mux orientation. The first two ports can be a master or a slave, but the default behavior is
 to be a slave. Port 1 and Port 2 are interchangeable. Each port operates the same way and
 has the same access in and out of the core. An interrupt mask is set for each that determines
 what events are interrupted on that given port.

16.3 I2C Address Setting

SWDIO : Serial Wire Debug http://www.arm.com/zh/products/system-ip/debug-trace/coresight-soc-components/serial-wire-debug.php